module MEMWB(clkIn,resetIn,signalsIn,resultIn,DataIn,Imm32In,retAddrIn,rdIn,signalsOut,resultOut,DataOut,Imm32Out,retAddrOut,rdOut);
  input clkIn; //from outside
  input resetIn; //from outside
  input[11:0] signalsIn; 
  input[31:0] resultIn; 
  input[31:0] DataIn; 
  input[31:0] Imm32In;
  input[31:0] retAddrIn;
  input[4:0] rdIn;
  output reg[11:0] signalsOut; 
  output reg[31:0] resultOut;
  output reg[31:0] DataOut;
  output reg[31:0] Imm32Out;
  output reg[31:0] retAddrOut; 
  output reg[4:0] rdOut;
  always @(posedge clkIn or negedge resetIn) begin
    if (!resetIn) begin 
      signalsOut<=0; 
      resultOut<=0;
      DataOut<=0;
      retAddrOut<=0;
      Imm32Out<=0;
      rdOut<=0;
      end
    else begin 
      signalsOut<=signalsIn; 
      resultOut<=resultIn;
      DataOut<=DataIn;
      retAddrOut<=retAddrIn;
      Imm32Out<=Imm32In;
      rdOut<=rdIn;
      end
    end
endmodule